2nd MIT-Toyohashi ASPIRE workshop 2025 Fall on November 25th at Science Tokyo.
Date: 25 November, 2025
Location: Conference Room L (2nd Floor), Science Tokyo Front (Kuramae-Kaikan、蔵前会館 2F 大会議室), Ookayama Campus, Institute of Science Tokyo
Program
**All programs are in JST (UTC+9)
| 10:00-10:15 | JST ASPIRE project introduction: Yukinori Sato (Toyohashi Univ. of Tech.) | |||
| 10:15-11:15 | “The Future of Fast Code: Giving Hardware What It Wants” Jonathan Ragan-Kelley (MIT) | |||
| 11:15-11:45 | “Efficient Stencil Computation with Temporal Blocking by Halide DSL” Toshio Endo (Science Tokyo) | |||
| 11:45-12:15 | “Loop and memory optimizations for accelerator design” Kenshu Seto (Kumamoto Univ) | |||
| 12:15-12:45 | Lunch Break | |||
| 12:45-13:45 | Poster presentations by students | |||
| 13:45-14:15 | “Quantifying Multi-Layer Dynamics and Telemetry-Driven Elasticity in the Post-5G Cloud Continuum” Irawan Widi Widayat (Toyohashi Univ of Tech) | |||
| 14:15-14:45 | “Highly Optimized Protocol Stacks with RISC-V Ecosystems for Cloud Computing and AI Systems” Hoku Ishibe (Toyohashi Univ of Tech) | |||
| 14:45-15:00 | Break | |||
| 15:00-15:30 | “Toward Sub-Microsecond Detection of Bragg Peaks Through Hardware-Level Optimization: Early Results on Groq Chip” Yugo Abe (Toyohashi Univ of Tech) | |||
| 15:30-16:00 | “Accelerating Distributed Tracing using SmartNICs” Ryuichi Sakamoto (Science Tokyo) | |||
| 16:00-16:30 | “Programming and optimizing applications for Edge-Cloud continuum with AI accelerators and SmartNIC” Yukinori Sato (Toyohashi Univ. of Tech.) | |||
| 16:30 | close | |||
Registration
Please make a registration from the following URL:
https://forms.gle/NAicqjzCUGUD5aUq9
A part of this tutorial will be supported by JST ASPIRE, Grant Number JPMJAP2430.
Project overview (in Japanese)
The Future of Fast Code: Giving Hardware What It Wants
Jonathan Ragan-Kelley (MIT)
Abstract: In the twilight of Moore’s Law, computer hardware has diverged from the programming models we use to control it. As a result, the performance and complexity gaps between “reasonable” programs and the fastest code is huge and growing. This talk will explore fundamental issues that drive hardware efficiency. From that foundation, it will highlight challenges and opportunities for the programming systems community in productively unlocking the potential of current and future hardware. Major themes include: leveraging domain-specific languages; balancing safety, automation, and control for high-performance programming; and broadening our understanding of “correctness” in a world of numerical programs and machine learning. I will conclude with a few thoughts on how to make an impact with programming systems research.
Bio: Jonathan Ragan-Kelley is Associate Professor of Electrical Engineering & Computer Science at MIT. He works on high-efficiency visual computing, including systems, languages, and compilers for graphics, vision, and machine learning. His work has been recognized by a Sloan fellowship as well as the ACM SIGGRAPH Significant New Researcher, NSF CAREER, and PLDI 10-year most influential paper awards. He was previously Assistant Professor of EECS at UC Berkeley, a visiting researcher at Google, a postdoc in Computer Science at Stanford, and earned his PhD in EECS from MIT in 2014. He co-created the Halide language and has helped build more than a dozen other DSL and compiler systems, the first of which was a finalist for an Academy technical achievement award.
Map
Ookayama Campus, Institute of Science Tokyo
Conference Room L (2nd Floor), Science Tokyo Front
(Kuramae-Kaikan、蔵前会館 2F 大会議室)